The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a nanosheet containing device (i.e., transistor) having a short gate length without exhibiting any sacrificial gate structure collapsing issues.
The use of non-planar semiconductor devices such as, for example, a nano sheet containing device is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions (i.e., nanosheets) having a vertical thickness that is substantially less than its width. Nanosheet containing device formation relies on the selective removal of one semiconductor material (e.g., a silicon germanium alloy) to another semiconductor material (e.g., silicon) to form suspended nanosheets for gate-all-around devices.
CMOS scaling of such nanosheet containing devices requires a reduction in gate length to accommodate a reduction of contract gate pitch. For example, for 5 nm node, the gate length target is about 15 nm for a contact gate pitch of about 44 nm.
Moreover, and during a source/drain epitaxy preclean step, an oxide etch is typically performed to clean the nanosheet region to ensure high quality epitaxy. In the active nanosheet regions, the sacrificial gate structures wrap around the nanosheets so that the sacrificial gate structures are mechanically stable. In other words, the nanosheets serve as an anchor to hold the sacrificial gate structures stable in the active region. In the isolation region, the sacrificial gate structures sit on a shallow trench isolation (STI) structure. It has been determined that the epitaxy preclean step undercuts the STI structure underneath the sacrificial gate structures causing the sacrificial gate structures to collapse in the isolation region. Sacrificial gate structure collapse causes defect and yield issues. There is thus a need for providing nanosheet transistors having a short gate length in which sacrificial gate structure collapsing issues have been mitigated.